mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 138

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

The PowerPC Core
6.3.4 Implementing the Precise Exception Model
To achieve maximum performance, many pieces of the instruction stream are concurrently
processed by the core independent of the sequence specified by the executing program.
Instructions execute in parallel and are completely random. The hardware ensures that this
out-of-order operation never has an effect different than that specified by the program. This
requirement is most difficult to assure when an interrupt occurs after instructions that
logically follow the faulting instruction or have already completed. At the time of an interrupt,
the machine state becomes visible to other processes and, therefore, must be in the
appropriate architecturally specified condition. The core takes care of this in the hardware
by automatically backing up the machine to the instruction which caused the interrupt and
is, therefore, said to implement a precise exception model. This is, of course, assuming that
the instruction causing the exception has not begun when the interrupt occurs.
To recover from an interrupt, a history buffer is used. This buffer is a FIFO queue that
records the relevant machine state at the time of each instruction issue. Instructions are
placed on the tail of the queue when they are issued and percolated to the head of the queue
while they are in execution. Instructions remain in the queue until they complete execution
and all preceding instructions have been completed to a point where no exception can be
generated (in the core, such a condition is fulfilled by waiting for full completion).
Hard Reset
System Reset
Machine Check Interrupt
Implementation Specific Instruction /
Data TLB Miss / Error Interrupts
Other Asynchronous Interrupts
(Noninstruction Related Interrupts)
Alignment Interrupt
Privileged Instruction
Trap
System Call Interrupt
Trace
Debug I- Breakpoint
Debug L- Breakpoint
Implementation Dependent Software
Emulation Interrupt
Floating-Point Unavailable
INTERRUPT TYPE
Freescale Semiconductor, Inc.
Table 6-2. Before and After Interrupts
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INSTRUCTION
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Any Privileged
Floating-Point
Load / Store
Load / Store
Instruction
tw, twi
TYPE
Any
Any
Any
Any
Any
Any
Any
NA
sc
BEFORE /
AFTER
Before
Before
Before
Before
Before
Before
Before
Before
Before
Before
After
After
After
NA
Undefined
Next Instruction to Execute
Faulting Instruction
Faulting Fetch or Load/Store
Next Instruction to Execute
Faulting Instruction
Faulting Instruction
Faulting Instruction
Next Instruction to Execute
Next Instruction to Execute
Faulting Instruction
Faulting Instruction + 4
Faulting Instruction
Faulting Instruction
CONTENTS OF SRR0
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