mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 727

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

You can program the CPM command register (CPCR) with the following commands to
receive data. After the hardware or software is reset and the channel is enabled by its
SCCM–ASYNC HDLC register, the channel is in receive enable mode and uses the first
buffer descriptor in the table.
16.9.19.11 SCCx ASYNC HDLC CONTROLLER ERRORS. The SCCx ASYNC HDLC
controller reports frame reception and transmission error conditions using the channel buffer
descriptors and the SCCE–ASYNC HDLC register. The following transmission error can be
detected by the SCCx ASYNC HDLC controller.
The following reception errors can be detected by the SCCx ASYNC HDLC controller.
• ENTER HUNT MODE — This command is used to force the SCCx ASYNC HDLC
• CLOSE RX BD—This command is not supported by the SCCx ASYNC HDLC
• INIT RX PARAMETERS—This command initializes all the receive parameters in this
• CTS Lost During Frame Transmission Error—When this error occurs, the channel stops
• Overrun Error—The SCCx ASYNC HDLC controller maintains an internal 8-byte FIFO
• CD Lost During Frame Reception Error—When this error occurs, the channel stops
• Abort Sequence Error—This error occurs when the SCCx ASYNC HDLC controller
controller to close the current RX buffer descriptor (if it is being used) and enter hunt
mode. The controller continues receiving after it finds a frame preceded by one or more
opening flags.
controller.
serial channel’s parameter RAM to their reset state and must only be issued when the
receiver is disabled. The INIT TX AND RX PARAMS command can also be used to
reset the receive and transmit parameters.
transmitting the buffer, closes it, sets the CT bit in the TX buffer descriptor and the TXE
bit in the SCCE–ASYNC HDLC. The channel continues transmitting from the next TX
buffer descriptor after the RESTART TRANSMIT command is issued.
when a serial communication controller receives data. A receive overrun occurs when
the communication processor module is unable to keep up with the data rate or the
SDMA channel is unable to write the received data to memory. The previous data byte
and the frame status are lost. The controller closes the buffer with the OV bit in the
buffer descriptor set and sets the RXF bit in the SCCE–ASYNC HDLC register. The
receiver then searches for the next frame.
receiving frames, closes the buffer, and sets the CD bit in the buffer descriptor and the
RXF bit in the SCCE–ASYNC HDLC register. This error has the highest priority. The
rest of the frame is lost and other errors are not checked in that frame. The receiver then
searches for the next frame once the CD signal is reasserted.
receives an abort sequence. At that time, the channel closes the buffer by setting the
AB bit in the RX buffer descriptor and sets the RXF bit in the SCCE–ASYNC HDLC
register. The CRC error status condition is not checked on aborted frames. If the abort
sequence is received and no frame is currently being received, the next buffer
descriptor is opened and then closed with the AB bit set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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