mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 151

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

PR—Problem State
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
FP—Floating-Point Available
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
ME—Machine Check Enable
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
FE0—Floating-Point Exception Mode 0
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
SE—Single-Step Trace Enable
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
BE—Branch Trace Enable
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
FE1—Floating-Point Exception Mode 1
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an rfi is executed.
Bit 24—Reserved
This bit is reserved and must be set to 0. It is loaded from the corresponding bit in the MSR
when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an
rfi is executed. Reserved bits in the MSR are set from the source value on write and return
the value last set for it on read.
IP—Interrupt Prefix
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The reset
value of this bit is determined by the hard reset configuration word. For more information,
see Section 4.3.1.1 Hard Reset Configuration Word.
IR—Instruction Relocate
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The
appropriate bit in the MSR is loaded from this bit when an
0 = The interrupt prefix is 0x000n_nnnn.
1 = The interrupt prefix is 0xFFFn_nnnn.
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is executed.
The PowerPC Core
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