mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1019

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

18.4.5 LCD Frame Buffer B Start Address Register
The 32-bit LCD frame buffer B start address (LCFBA) register contains the start address of
the frame buffer data that you want to send to your LCD dual-scan panel (lower half). FIFO
B is the destination for your frame buffer data to be passed to the lower half of the panel.
Notice that for single-scan panels, FIFO B is concatenated with FIFO A to transfer data, so
only the LCFAA register needs to be loaded. However, for dual-scan panels, the LCFBA
register must be set. For dual-scan panels, the DMA controller uses the buffer B start
address to initiate data transfers from display memory (system memory or a dedicated
display memory block) to FIFO B. Because all LCD controller DMA bursts must be 16-byte
aligned, the four least-significant bits of the address are not used. This register is read by
the LCD controller at the start of each frame. Therefore, changing this register will not take
effect until the WBF bit expires.
FBA—FIFO B Address
This field designates the start address in display or system memory where the LCD panel
data resides. The data retrieved is for the lower half of a dual-scan panel and passes
through FIFO B.
LCFBA
NOTE: X - “Don’t Care” and — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
16
0
17
1
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
FBA
R/W
—
(IMMR & 0xFFFF0000) + 0x854
IMMR & 0xFFFF0000 + 0x856
22
6
23
7
FBA
R/W
—
24
8
25
9
10
26
11
27
12
28
13
29
LCD Controller
R/W
—
X
14
30
18-27
15
31