mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1321

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Index
data cache address register,
data cache control and status register,
data cache,
data cache, how to flush and invalidate,
data sampling,
DC_ADR,
DC_CST,
dcbf,
dcbi,
dcbst,
dcbt,
dcbtst,
dcbz,
debug mode
DEC,
decoding data, with a DPLL,
decrementer register,
decrementer,
DEMOD
DEMOD,
DER,
development capabilities
freeze,
how to enable and disable,
implementation-specific operations,
instructions,
operation,
organization,
programming,
read,
reading,
registers
write,
entering,
applications,
function descriptor,
modulation table, sample data buffers, and AGC
parameter packet,
development system interface
development system interface,
features,
program flow tracking
20-1
10-14
10-14
10-14
10-14
6-16
constants,
6-17
10-14
10-14
special,
debug mode support,
development interface port shift register,
development port,
trap enable control register,
trap enable mode,
instruction fetch show cycle control,
operation
16-62
10-10
10-10
30
10-5
10-7
,
,
10-12
,
,
12-13
20-57
compressing cancelled instructions,
10-1
,
10-14
11-48
11-48
,
11-48
20-26
20-1
12-12
8
11-48
10-10
15-64
10-4
10-3
16-63
16-65
10-2
10-3
,
12-13
10-14
16-64
16-63
20-29
20-22
Freescale Semiconductor, Inc.
16-193
10-7
20-22
For More Information On This Product,
10-13
20-20
MPC823 REFERENCE MANUAL
20-31
10-5
10-4
10-13
Go to: www.freescale.com
20-8
20-
20-
development port configuration,
development port,
DFNH,
DFNL,
dialog,
differences
differential Manchester,
digital phase-locked loop,
digital signal processing,
disable timer mechanism,
disabling
DMA
DMA controller
DMA, video controller,
DP0,
DP1,
DP2,
DP3,
DPDR,
DPIR,
DPIR/DPDR,
program flow tracking,
programming
programming,
software monitor debugger support
software monitor debugger support,
watchpoints and breakpoints
watchpoints and breakpoints,
between autobuffer and buffer chaining,
HDLC and ASYNC HDLC,
all modules,
idle sequence function,
part of SCCx receiver,
part of SCCx transmitter,
part of SMC receiver,
part of SMC transmitter,
SCCs,
SCCx receiver,
SCCx transmitter,
SMC receiver,
SMC transmitter,
SMC,
PCMCIA,
memory map,
2-3
2-3
2-4
2-4
6-17
5-17
16-263
5-17
6-17 20-60
operation,
debug mode registers,
development port data registers,
development port registers,
protecting the registers,
freeze indication,
examples,
internal,
operation,
16-387
16-196
external hardware,
internal hardware,
17-8
20-9
16-196
3-5
20-41
20-3
20-16
20-29
20-13
16-388
16-197
16-388
16-196
19-4
16-194
16-26
20-41
16-389
16-190
15-43
20-2
16-197
16-212
16-388
16-196
20-3
16-283
20-55
20-5
20-41
4-7
,
15-64
20-8
20-42
MOTOROLA
20-40
20-60
16-96