mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 89

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Reset
4.1 TYPES OF RESET
The MPC823 has several types of inputs to the reset logic:
All of these reset sources are fed into the reset controller and, depending on the source of
the reset, different actions are taken. The reset status register reflects the last source to
cause a reset.
4.1.1 Power-On Reset
PORESET (power-on reset) is an active low input pin. In a system with power-down
low-power mode, this pin must only be activated when a voltage in the keep-alive power
(KAPWR) rail fails. When this pin is asserted, the MODCK bits are sampled and the
phase-locked loop multiplication factor and pitrtclk and tmbclk sources are changed to their
default values. When this pin is negated, internal MODCK values are unchanged. The
PORESET pin must be asserted for a minimum of 3 microseconds. After detecting this
assertion, the MPC823 enters the power-on reset state and stays there until the following
events occur:
When PORESET is asserted, the MPC823 enters the power-on reset (POR) state in which
SRESET and HRESET are asserted by the core. When the MPC823 remains in POR, the
extension counter of 512 is reset, and the MODCK pins are sampled when POR pin is
negated. After the negation of PORESET and the PLL locks, the core enters the state of
internal initiated HRESET and continues driving the HRESET and SRESET pins for 512
cycles. When the timer expires, which is usually after the 512 cycles, the configuration is
sampled from the data pins and the core stops driving the pins. An external pull-up resistor
should drive the HRESET and SRESET pins high. After the pins are negated, a 16-cycle
period passes before the presence of an external (hard/soft) reset is tested. Refer to
Section 4.3.1 Hard Reset for more information.
• Power-on reset
• External hard reset
• Internal hard reset
• External soft reset
• Internal soft reset
• The internal PLL enters the lock state and the system clock is active
• The PORESET pin is negated
Loss of lock
Software watchdog reset
Checkstop reset
Debug port hard reset
JTAG reset
Debug port soft reset
JTAG soft reset
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
MOTOROLA