mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 255

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Memory Management Unit
11.6.2.1 MMU DATA CAM ENTRY READ REGISTER. When the content-addressable
memory of the MMU data CAM entry read (MD_CAM) register is read, it contains the
effective address and page sizes of an entry indexed by the DTLB_INDX field of the
MD_CTR. This register is only updated when you write a value to it.
EPN—Effective Page Number
These bits are the most-significant bits of the page’s effective address.
SPVF—Subpage Validity Flags
MD_CAM
NOTE: — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
For Bit 20:
0 = Subpage 0 (address[20:21] = 00) is not valid.
1 = Subpage 0 (address[20:21] = 00) is valid.
For Bit 21:
0 = Subpage 1 (address[20:21] = 01) is not valid.
1 = Subpage 1 (address[20:21] = 01) is valid.
For Bit 22:
0 = Subpage 2 (address[20:21] = 10) is not valid.
1 = Subpage 2 (address[20:21] = 10) is valid.
For Bit 23:
0 = Subpage 3 (address[20:21] = 11) is not valid.
1 = Subpage 3 (address[20:21] = 11) is valid.
16
0
17
1
EPN
R
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
SPVF
R
22
6
23
SPR 824
SPR 824
7
EPN
R
24
8
PS
25
R
9
10
26
SH
11
27
R
12
28
13
29
ASID
R
MOTOROLA
14
30
15
31

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