mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 168

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

The features of the MMU hardware is as follows:
7.3.4 Reference and Change Bits
No reference bit is supported by the MPC823. However, the change bit is supported by
using the data TLB error interrupt mechanism when writing to an unmodified page.
7.3.5 Storage Protection
Two main protection modes are supported by the MPC823:
For more details, refer to Section 11 Memory Management Unit.
7.3.6 Storage Control Instructions
7.3.6.1 DATA CACHE BLOCK INVALIDATE (dcbi). This instruction is executed
according to the definition in PowerPC Operating Environment Architecture (Book III) .
7.3.6.2 TLB INVALIDATE ENTRY (tlbie). This instruction is performed as defined by the
architecture, except that the 22 most-significant bits of the EA are used for address
compare.
7.3.6.3 TLB INVALIDATE ALL (tlbia). This instruction is performed as defined by the
architecture.
7.3.6.4 TLB SYNCHRONIZE (tlbsync). This instruction is implemented like a regular
mtspr instruction as it relates to engine synchronization with no further effects.
7.3.7 Interrupts
7.3.7.1 CLASSES. All interrupts associated with storage are implemented as precise
interrupts by the core, which means that a load/store instruction is not complete until all
possible error indications are sampled from the load/store bus. This also implies that a store
or nonspeculative load instruction is not issued to the load/store bus until all previous
instructions have completed. If a late error occurs, a store cycle (or a nonspeculative load
cycle) can be issued and aborted.
7.3.7.2 PROCESSING. In each interrupt handler, when registers SRR0 and SSR1 are
saved, MSR
• 8-entry fully associative instruction TLB
• 8-entry fully associative data TLB
• Supports up to 16 virtual address spaces
• Supports 16 access protection groups
• Supports fast software tablewalk mechanism
• Domain manager mode
• PowerPC mode
RI
can be set to 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
PowerPC Architecture Compliance
7-7