mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 692

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
FSE—Flag Sharing Enable.
This bit is only valid if the RTSM bit is set in the GSMR_H. This bit can be modified on-the-fly.
DRT—Disable Receiver While Transmitting
BUS—HDLC Bus Mode
BRM—HDLC Bus RTS Mode
This bit is only valid if the BUS bit is set to 1. Otherwise, it is ignored.
MFF—Multiple Frames in FIFO
0 = Normal operation.
1 = If the NOF0–NOF3 field is set to 0000, then a single shared flag is transmitted
0 = Normal operation.
1 = While data is being transmitted by a serial communication controller, the receiver
0 = Normal HDLC operation.
1 = HDLC bus operation is selected. Refer to Section 16.9.17 The HDLC Bus
0 = Normal RTSx operation during HDLC bus mode. RTSx is asserted on the first bit
1 = Special RTSx operation during HDLC bus mode. RTSx is delayed by one bit with
0 = Normal operation. The transmit FIFO must never contain more than one HDLC
1 = The transmit FIFO can contain multiple frames, but lost CTSx is not guaranteed to
between back-to-back frames. Other values of NOF0–NOF3 are decremented by
1 when this bit is set. This is useful in Signaling System #7 (SS#7) applications.
is disabled. This configuration is useful if the HDLC channel is configured onto a
multidrop line and you do not want to receive your own transmission.
Controller for more details.
of the transmit frame and negated after the first collision bit is received.
respect to the normal case. This is useful when the HDLC bus protocol is being run
locally and transmitted over a long-distance transmission line at the same time.
Data can be delayed one bit before it is sent over the transmission line, thus RTSx
can be used to enable the transmission line buffers. The result is a clean signal
level sent over the transmission line.
frame. The CTSx lost status is reported accurately on a per-frame basis. The
receiver is not affected by this bit.
be reported on the exact buffer/frame it truly occurred on. This option, however,
can improve the performance of HDLC transmissions of small back-to-back frames
or in cases where you prefer to limit the number of flags transmitted between
frames. The receiver is not affected by this bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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