mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1320

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

connecting MPC823 to external peripheral,
connecting the MPC823 to an SRAM device,
connecting the MPC823 to memory device,
connecting the MPC823 to static RAM memory,
connecting UPM RAM array to DRAM,
connections
content-addressable memory,
control byte,
control field,
control frames,
copyback mode,
core
core,
cost, reduction,
COUNTA,
COUNTB,
CPCR,
CPM command register,
CPM interrupt controller
38
port B example,
power-on reset clock (table),
reset,
SCCx in ASYNC HDLC mode,
SCCx in Ethernet mode,
system endian,
system interface unit,
TDM with dynamic frames,
TDM with static frames,
time-slot assigner,
UPMA,
UPMB,
IrDA,
SCCx in AppleTalk mode,
to the time-slot assigner,
basic instruction pipeline,
basic structure,
block diagram,
features,
instruction flow,
register unit
register unit,
sequencer unit
sequencer unit,
configuration register (CICR),
16-495
6-1
16-9
control registers,
external interrupt,
flow control,
interrrupt ordering,
interrupt processing,
interrupts,
issuing instructions,
precise exception model,
serialization,
16-195
4-7
20-53
20-54
15-19
15-22
16-270
16-262
6-1
16-262
5-12
10-11
6-15
6-7
6-3
14-1
6-2
6-2
6-4
16-486
6-5
6-12
16-114
16-9
6-16
12-2
6-13
6-14
16-118
6-6
Freescale Semiconductor, Inc.
16-327
16-117
6-11
6-4
16-264
16-162
For More Information On This Product,
16-119
5-13
6-8
16-503
16-273
MPC823 REFERENCE MANUAL
15-76
Go to: www.freescale.com
15-31
15-29
15-38
15-
CPM,
CR,
CRC (definition),
CS output configurations,
CS,
CS2,
CS3,
CS6,
CS7,
CSMA/CD,
CTS2,
CTS3,
cycle types,
cyclic redundancy check,
D
DAR,
data cache
features,
in-service register (CISR),
interrupt mask register (CIMR),
interrupt pending register (CIPR),
interrupt structure (illustration),
interrupt vector register (CIVR),
interrupt vectors
interrupt vectors,
interrupts,
masking interrupts,
operation,
PC6 example,
programming,
source priorities
source priorities,
USB example,
block diagram,
cache-inhibited accesses,
coherency,
commands
commands,
data path block diagram,
debug support,
features,
15-55
6-19
2-6
2-6
2-4
2-5
6-16
16-1
2-10
2-9
encoding,
highest priority interrupt,
nested interrupts,
USB and SCC2 relative priority,
CACHE LINE FLUSH,
COPYBACK,
DATA CACHE DISABLE,
DATA CACHE ENABLE,
INVALIDATE ALL,
LOCK LINE,
UNLOCK ALL,
UNLOCK LINE,
,
6-22
,
,
16-315
2-11
7-10
15-41
16-497
16-508
16-495
10-13
10-13
16-230
16-502
16-503
16-508
16-509
10-2
10-12
10-13
16-497
16-501
10-13
10-13
16-500
10-13
16-230
15-29
16-500
10-13
10-3
10-12
16-507
10-13
16-498
10-13
10-13
16-496
16-506
16-508
16-505
16-498
Index-7
Index