mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 888

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
RFCR
TFCR
RESET
RESET
• RFCR and TFCR—The receive and transmit function code register entries contain the
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
value that you want to appear on the AT pins when the associated SDMA channel
accesses memory. This register controls the byte-ordering convention used in the
transfers.
Bits 0–2—Reserved
These bits are reserved and must be set to 0.
BO—Byte Ordering
You must set these bits to select the required byte ordering of the data buffer.
AT—Address Type 1–3
These bits contain the function code value used during the SDMA channel memory
access. AT0 is driven with a 1 to identify this SDMA channel access as a DMA-type
access.
00 = The DEC/Intel convention is used for byte ordering (swapped operation) and
01 = PowerPC little-endian byte ordering. As data is transmitted onto the serial line
1X = Motorola byte ordering (normal operation) is also called big-endian byte
0
is also called little-endian byte ordering. The transmission order of bytes within
a buffer word is reversed in comparison to the Motorola mode. This mode is
supported only for 32-bit port size memory.
from the data buffer, the least-significant byte of the buffer double-word
contains data to be transmitted earlier than the most-significant byte of the
same buffer double-word.
ordering. As data is transmitted onto the serial line from the data buffer, the
most-significant byte of the buffer word contains data to be transmitted earlier
than the least-significant byte of the same buffer word.
0
RESERVED
RESERVED
R/W
R/W
Freescale Semiconductor, Inc.
1
0
1
0
For More Information On This Product,
MPC823 REFERENCE MANUAL
2
2
Go to: www.freescale.com
SPI BASE + 0x04
SPI BASE + 0x05
3
3
R/W
R/W
BO
BO
0
0
4
4
5
5
R/W
R/W
AT
AT
6
0
6
0
MOTOROLA
7
7