mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 409

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

LOOP—Loop
The first RAM word in the RAM array where LOOP is 1 is recognized as the Loop Start Word.
The next RAM word where LOOP is 1 is recognized as the Loop End Word. The RAM words
between the beginning and end are defined as the loop. The UPM executes this loop as
many times as it is defined in the corresponding LOOP field of the MxMR.
EXEN—Exception Enable
When an external device asserts the TEA or RESET signals, this bit allows you to branch to
the exception start address (EXS) where you would store your exception handler. The
exception start address is found at a fixed address in the RAM array.
AMX—Address Multiplexing
This bit determines the source of the A[6:31] signals.
NA—Next Address
This bit determines how much the current address is incremented.
0 = The current RAM word is not the start or end of a loop construct.
1 = The current RAM word is the start or end of a loop construct.
0 = The UPM continues executing the remaining RAM words.
1 = The current RAM word allows a branch to an exception handler after the current
00 = The value of the A[6:31] signals at the trailing edge of GCLK1 is the address that
01 = Reserved.
10 = The value of the A[6:31] signals at the trailing edge of GCLK1 is the address that
11 = The value of the A[6:31] signals at the trailing edge of GCLK1 is the contents of
0 = The address increment is disabled.
1 = In conjunction with the PS field in the base register, the increment value of the
— If the accessed bank has a 32-bit port size, the value of the A[28:31] signals are
— If the accessed bank has a 16-bit port size, the value of the A[28:31] signals are
— If the accessed bank has an 8-bit port size, the value of the A[28:31] signals are
cycle if an exception condition is detected. The exception condition can be an
external device asserting TEA, HRESET, or SRESET.
A[28:31] signals at the trailing edge of GCLK1 is as follows:
is requested by the internal master. For example, column address.
is requested by the internal master multiplexed according to the AMA/AMB field
of the MxMR. For example, row address.
the memory address register (MAR). For example, SDRAM mode initialization.
incremented by 4.
incremented by 2.
incremented by 1.
Note: The value of the NA bit is only relevant when the UPM serves a burst-read or
burst-write request. Under other patterns this bit is reserved.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Memory Controller
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