mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 681

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.15.22 S-RECORD PROGRAMMING EXAMPLE.The following is an example of a
downloading application that uses a SCCx channel as a UART controller. The application
performs S-record downloads and uploads between a host computer and an intelligent
peripheral through a serial asynchronous line. The S-records are strings of ASCII characters
that begin with ‘S’ and end in an end-of-line character. This characteristic is used to impose
a message structure on the communication between the devices. Each device can transmit
XON and XOFF characters for flow control, which do not form part of the program being
uploaded or downloaded.
The PSMR—SCC UART register must be set as needed with the FRZ bit cleared and the
ENT and ENR bits set. Receive buffers must be linked to the receive buffer table with the I
bit set. For simplicity, assume that the line is not multidrop (no addresses are transmitted)
and that each S-record fits into a single data buffer. Three characters must first be entered
into the SCCx UART control character table:
To receive the S-records, the core must only wait for the receive interrupt, thus indicating
that a complete S-record buffer has been received. Transmission requires assembling
S-records into data buffers and linking them to the transmit buffer table and it can be
temporarily stopped when an XOFF character is received. This scheme minimizes the
number of interrupts received by the core (one per S-record) and relieves it from the task of
continually scanning for control characters.
• Line Feed—Both the E and R bits must be cleared. When an end-of-line character is
• XOFF—E must be cleared and R must be set. Whenever the core receives a control
• XON—This character must be received after XOFF. The E bit must be cleared and the
received, the current buffer is closed and made available to the core for processing.
This buffer contains an entire S-record that the processor can now check and copy to
memory or disk as required.
character received interrupt and the receive control character register contains XOFF,
the software must immediately stop transmitting to the other station by setting the FRZ
bit in the PSMR–SCC UART. This prevents data from being lost by the other station
when it runs out of receive buffers.
R bit must be set. The FRZ bit on the transmitter must now be cleared. The
communication processor module automatically resumes transmission of the serial line
at the point at which it was previously stopped. Like XOFF, the XON character is not
stored in the receive buffer.
Note: After 16 bytes are transmitted, the TX buffer descriptor is closed. Additionally,
the receive buffer is closed after 16 bytes are received. Any data received after
16 bytes causes a busy (out-of-buffers) condition since only one RX buffer
descriptor is prepared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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