mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1135

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
IEEE 1149.1 Test Access Port
21.3.2 The sample/preload Instruction
The sample/preload instruction initializes the boundary scan register output cells before
extest is selected. This initialization ensures that known data will appear on the outputs
when entering the extest instruction. The sample/preload instruction also provides an
opportunity to obtain a snapshot of system data and control signals.
21.3.3 The bypass Instruction
The bypass instruction creates a shift register path from TDI to the bypass register and,
finally, to the TDO pins, thus circumventing the 397-bit boundary scan register. This
instruction is used to enhance test efficiency when a component other than the MPC823 is
the device being tested. It selects the single-bit bypass register as illustrated in Figure 21-7.
When the bypass register is selected by the current instruction, the shift register stage is set
to a logic zero on the rising edge of the TCK pin in the capture-DR controller state.
Therefore, the first bit to be shifted out after selecting the bypass register is always a logic
zero.
21.3.4 The clamp Instruction
The clamp instruction selects the single-bit bypass register as illustrated in Figure 21-7
above, and the state of all signals driven from the system output pins is completely defined
by the data previously shifted into the boundary scan register.
21.3.5 The hi-z Instruction
The hi-z instruction is provided as a manufacturer’s optional public instruction/On to avoid
back driving the output pins during circuit board testing. When
drivers, including the two-state drivers, are turned off (high impedance). The instructIon
selects the bypass register.
Note: Since there is no internal synchronization between the TCK and CLKOUT, you
FROM TDI
SHIFT DR
must provide some form of external synchronization between the JTAG
operation TCK frequency and system operation CLKOUT frequency to achieve
meaningful results.
Freescale Semiconductor, Inc.
0
For More Information On This Product,
Figure 21-7. Bypass Register
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
G1
1
1
MUX
CLOCK DR
D
C
TO TDO
is invoked all output
MOTOROLA

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