mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 760

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
W—Wrap (Final Buffer Descriptor in Table)
I—Interrupt
L—Last in Frame
This bit is set by the SCCx Transparent controller when this buffer is the last in a frame. If
CD in envelope mode is negated or an error has been received, one or more of the OV, CD,
and DE bits are set. The SCCx Transparent controller writes the number of frame octets to
the DATA LENGTH field.
F—First in Frame
The SCCx Transparent controller sets this bit when this buffer is the first in the frame:
CM—Continuous Mode
DE—DPLL Error
This bit is set by the SCCx Transparent controller when a DPLL error occurs while this buffer
is being received. In decoding modes, where a transition occurs on every bit, the DPLL error
is set when a missing transition occurs.
NO—RX Non-Octet
This bit indicates that a frame containing a number of bits not exactly divisible by eight is
received.
0 = This is not the last buffer descriptor in the RX buffer descriptor table.
1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer
0 = No interrupt is generated after this buffer is used.
1 = When this buffer is closed by the transparent controller, the RX bit in the
0 = This buffer is not the last one in a frame.
1 = This buffer is the last one in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
0 = Normal operation.
1 = The E bit is not cleared by the communication processor module after this buffer
is used, the communication processor module receives incoming data into the first
buffer descriptor that RBASE points to in the table. The number of RX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
SCCE–Transparent register is set. The RX bit can cause an interrupt if it is
enabled.
descriptor is closed, thus allowing the associated data buffer to be automatically
overwritten next time the communication processor module accesses this buffer
descriptor. However, the E bit is cleared if an error occurs during reception,
regardless of how the CM bit is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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