mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 766

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.21.14 SCC2 TRANSPARENT PROGRAMMING EXAMPLE. The following is an
example initialization sequence for SCC2 in transparent mode. The transmitter and receiver
are both enabled, but operate independently of each other. They implement the connection
illustrated on MPC823 (B) in Figure 16-103. The transmit and receive clocks are externally
provided to MPC823 (B) using the CLK3 pin. The SCC2 Transparent controller is configured
with the RTS2 and CD2 pins active and CTS2 is grounded internally by the configuration in
port C. A 16-bit CRC-CCITT is sent with each transparent frame. The FIFOs are configured
for fast operation.
1. Configure the port A pins to enable the TXD2 and RXD2 pins. Write PAPAR bits 13
2. Configure the port C pins to enable RTS2, CTS2, and CD2. Write PCPAR bit 14 with
3. Configure port A to enable the CLK3 pin. Write PAPAR bit 5 with a one and PADIR
4. Connect the CLK3 pin to the SCC2 using the serial interface. Write the R2CS and
5. Connect the SCC2 to the NMSI and clear the SC2 bit of the SICR.
6. Write the SDCR with the appropriate arbitration ID.
7. Write RBASE and TBASE in the SCCx parameter RAM to point to the RX buffer
8. Program the CPCR to execute the INIT RX AND TX PARAMS command for the
9. Write RFCR and TFCR with 0x18 for normal operation.
10. Write MRBLR with the maximum number of bytes per receive buffer and assume 16
11. Write CRC_P with 0x0000FFFF to comply with the 16-bit CRC-CCITT.
12. Write CRC_C with 0x0000F0B8 to comply with the 16-bit CRC-CCITT.
13. Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main
14. Initialize the TX buffer descriptor. Assume the TX data buffer is at 0x00002000 in main
15. Write 0xFFFF to the SCCE–Transparent to clear any previous events.
16. Write 0x0013 to the SCCM–Transparent to enable the TXE, TX, and RX interrupts.
17. Write 0x20000000 to the CIMR so the SCC2 can generate a system interrupt. The
18. Write 0x00001980 to the GSMR_H to configure the transparent channel.
and 12 with ones and then PADIR and PAODR bits 13 and 12 with zeros.
one and bits 8 and 9 with zero, PCDIR bits 14, 9, and 8 with zero, and PCSO bits 8
and 9 with one.
bit 5 with a zero.
T2CS bits of the SICR to 110.
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of dual-port RAM and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
SCC2. To execute this command for SCC2, write 0x0041 to the CPCR.
bytes, so MRBLR = 0x0010.
memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional), and
0x00001000 to RX_BD_Pointer.
memory and contains five 8-bit characters. Write 0xBC00 to TX_BD_Status, 0x0005
to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
CICR must also be initialized.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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