mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 263

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Memory Management Unit
SFP—Privileged (Supervisor) Fetch Permission
11.6.3.3 MMU INSTRUCTION RAM ENTRY READ REGISTER 1. The MMU instruction
RAM entry read register 1 (MI_RAM1) contains the protection mode information of the entry
indexed by the ITLB_INDX field of the MI_CTR. This register is only updated when you write
to the MI_CAM register.
Bits 0–25—Reserved
These bits are reserved and must be set to zero.
MI_RAM1
NOTE: — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
Bit 28:
0 = Subpage 0 (address[20:21]=00) privileged fetch is not permitted.
1 = Subpage 0 (address[20:21]=00) privileged fetch is permitted.
Bit 29:
0 = Subpage 1 (address[20:21]=01) privileged fetch is not permitted.
1 = Subpage 1 (address[20:21]=01) privileged fetch is permitted.
Bit 30:
0 = Subpage 2 (address[20:21]=10) privileged fetch is not permitted.
1 = Subpage 2 (address[20:21]=10) privileged fetch is permitted.
Bit 31:
0 = Subpage 3 (address[20:21]=11) privileged fetch is not permitted.
1 = Subpage 3 (address[20:21]=11) privileged fetch is permitted.
16
0
17
1
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
RESERVED
20
MPC823 REFERENCE MANUAL
4
R
0
Go to: www.freescale.com
21
5
22
6
RESERVED
23
SPR 818
SPR 818
7
R
0
24
8
25
9
10
26
11
27
UFP
—
R
12
28
13
29
MOTOROLA
PV
14
30
—
R
15
31
—
G
R