mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 173

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

PowerPC Architecture Compliance
7.3.7.3.10 Implementation-Dependent Software Emulation Interrupt. An
implementation-dependent software emulation interrupt occurs as a result of one of the
following conditions:
In addition, the following registers are set:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
SRR1—Save/Restore Register 1
MSR—Machine State Register
Execution resumes at offset x’01000’ from the base address indicated by MSR
7.3.7.3.11 Implementation-Specific Instruction TLB Miss Interrupt. This type of
interrupt occurs if MSR
page number cannot be translated by TLB. The following registers are set:
SRR0–Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
• When executing any unimplemented instruction, including all illegal and
• When executing a mtspr or mfspr that specifies an on-core unimplemented register,
• When executing a mtspr or mfspr that specifies an off-core unimplemented register
unimplemented optional and floating-point instructions.
regardless of SPR
and SPR
to Section 7.3.7.3.6 Program Interrupt.
1–4
10–15
Other
IP
ME
LE
Other
0
Set to 0.
Set to 0.
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
No change.
No change.
Bits are copied from the ILE.
Set to 0.
Note: The exception 1000 implementation-dependent software emulation is triggered
=0 or MSR
when an unimplemented opcode is being decoded.
0
IR
Freescale Semiconductor, Inc.
.
=1 and you try to fetch an instruction from a page whose effective
PR
For More Information On This Product,
=0 (no program interrupt condition). For more information, refer
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
IP
MOTOROLA
.
RI
.