mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 678

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
BRKS—Break Start
If set, this bit indicates when a break character is received. It is the first break of a break
sequence. You do not receive multiple BRKS events if a long break sequence is received.
CCR—Control Character Received
If set, this bit indicates when a control character is received and stored in the RCCRP of the
SCCx UART parameter RAM.
BSY—Busy Condition
If set, this bit indicates that a character has been received and discarded due to a lack of
buffers. If multidrop mode is selected, the receiver automatically enters hunt mode.
Otherwise, reception continues as soon as an empty buffer is provided. The latest point that
an RX buffer descriptor can be changed to empty and still guarantee that a busy condition
will be avoided, is the middle of the stop bit of the first character to be stored in that buffer.
TX—TX Buffer
If set, this bit indicates that a buffer has been transmitted over the UART channel. If the CR
bit is set to 1 in the TX buffer descriptor, this bit is set no sooner than when the last stop bit
of the last character in the buffer is first transmitted. If CR is set to 0, this bit is set after the
last character is written to the transmit FIFO.
RX—RX Buffer
If set, this bit indicates that a buffer has been received over the UART channel. This event
occurs no sooner than the middle of the first stop bit of the character that caused the buffer
to close.
16.9.15.19 SCCx UART MASK REGISTER.When a serial communication controller is in
UART mode, the 16-bit, read/write SCCx mask register is referred to as the SCCx UART
mask register (SCCM–UART). It has the same bit formats as the SCCE–UART register. If a
bit in this register is a 1, the corresponding interrupt in the SCCE–UART register is enabled.
If it is zero, the corresponding interrupt is masked.
SCCM–UART
RESET
FIELD
ADDR
R/W
BIT
0
RESERVED
R/W
1
0
2
Freescale Semiconductor, Inc.
For More Information On This Product,
GLR
R/W
3
0
GLT
R/W
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
RES
R/W
5
0
R/W
AB
6
0
(IMMR & 0xFFFF0000) + 0x
R/W
IDL
7
0
GRA
R/W
8
0
A34
BRKE
R/W
9
0
BRKS
R/W
10
0
RES
R/W
11
0
CCR
R/W
12
0
BSY
R/W
13
0
MOTOROLA
R/W
14
TX
0
R/W
15
RX
0