mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 72

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Signals
Power Supply
SHIFT/CLK
SIGNAL
FRAME
VSYNC
HSYNC
DSDO
LOAD
DSCK
PD[5]
PD[4]
PD[3]
TRST
DSDI
TMS
TDO
CLK
TCK
N/C
TDI
PIN NUMBER
See Table 2-2
See Table 2-2
breakout.
breakout.
for pin
for pin
R12
R11
N12
P11
T12
P2
P3
N4
Table 2-1. Signal Descriptions (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
General-Purpose I/O Port D Bit 5—Bit 5 of the general-purpose I/O port D.
FRAME—The output signal from the video controller that marks the beginning of a
new frame.
VSYNC—The output signal from the LCD controller that marks the beginning of a
new frame.
General-Purpose I/O Port D Bit 4—Bit 4 of the general-purpose I/O port D.
LOAD—The output signal from the video controller that marks the beginning of a
new display line.
HSYNC—The output signal from the LCD controller that marks the beginning of a
new frame.
General-purpose I/O Port D Bit 3—Bit 3 of the general-purpose I/O port D.
SHIFT/CLK—This output signal is used to generate the shift clock timing to the LCD
panel when using the LCD controller. The direction is defined when you program it.
CLK—When the video controller is used, the CLK function can either be an output
clock to drive the video encoder or an external input clock from the video encoder to
drive the video controller. The direction is defined when you program it.
VDDL—Power supply of the internal logic.
VDDH—Power supply of the I/O buffers and certain parts of the clock control.
VDDSYN—Power supply of the phase-locked loop circuitry.
VSSSYN—Power supply of the phase-locked loop ground.
VSSSYN1—Power supply of the phase-locked loop ground.
GND—Power supply ground.
KAPWR—Power supply of the internal oscillator, real-time clock, periodic interrupt
timer, decrementer, and timebase.
Test Clock—This input signal is the clock of the JTAG interface.
Development Serial Clock—This input signal is the clock for the debug port
interface.
Test Mode Select—This input signal controls the TAP machine sequence in the
JTAG interface.
Test Data Input—This input signal is the data in the JTAG interface.
Development Serial Data Input—This input signal is the data for the debug port
interface.
Test Data Output—This three-state output signal is the data out of the JTAG
interface.
Development Serial Data Output—This output signal is the data out of the debug
port interface.
Test Reset—This input signal is the asynchronous reset of the TAP machine on the
JTAG interface.
No Connect—These pins are not connected.
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
DESCRIPTION
MOTOROLA