mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 211

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Data Cache
The DC_ADR must be configured into the following fields before the internal parts of the
data cache are read from the DC_DAT register.
Bits 0–17, 20–22 and 30–31—Reserved
These bits are reserved and must be set to 0.
RT—Register or Tag Selection
WAY—Way Selection
SET—Set Selection
This field is used to select the index of the cache array. When RT is set to 1, it specifies the
register to be read. The following registers and their encoding are supported:
WORD—Word Selection
This field is used to select a word within a set and way.
DC_ADR (CACHE READ COMMAND FORMAT)
NOTE: — = Undefined.
RESET
RESET
FIELD
FIELD
• 0 00—Copyback data register 0
• 0 01—Copyback data register 1
• 0 02—Copyback data register 2
• 0 03—Copyback data register 3
• 0 04—Copyback address register
SPR
SPR
R/W
R/W
BIT
BIT
0 = Select tag operation.
1 = Select register operation.
0 = Select Way 0 of the cache array.
1 = Select Way 1 of the cache array.
RESERVED
16
0
R/W
—
17
1
R/W
RT
18
—
2
Freescale Semiconductor, Inc.
WAY
R/W
For More Information On This Product,
19
—
3
20
MPC823 REFERENCE MANUAL
4
RESERVED
Go to: www.freescale.com
R/W
21
—
5
22
6
RESERVED
23
7
R/W
569
569
—
24
8
SET
R/W
25
—
9
10
26
11
27
12
28
WORD
R/W
—
13
29
MOTOROLA
RESERVED
14
30
R/W
—
15
31