mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1328

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

instructions (cancelled), compression of,
instructions, class,
orc,
order storage access,
ori,
oris,
rfi,
rlwimi,
rlwinm,
rlwnm,
sample/preload,
sc,
slw,
sraw,
srawi,
srw,
stb,
stbu,
stbux,
stbx,
sth,
sthbrx,
sthu,
sthux,
sthx,
stmw,
storage control,
storage synchronization,
string,
stswi,
stswx,
stw,
stwbrx,
stwcx,
stwu,
stwux,
stwx,
subf,
subfc,
subfe,
subfic,
subfme,
subfze,
sync,
synchronize,
system call,
timing list,
tlbia,
tlbie,
tlbsync,
tw,
twi,
xor,
xori,
xoris,
B-115
B-122
B-156
B-113
B-157
B-127
B-131
B-112
B-158
B-123
B-139
B-126
B-114
B-159
B-130
B-135
B-153
B-154
B-128
B-133
B-146
B-145
B-143
B-152
B-124
B-160
B-137
B-125
B-136
B-129
B-134
B-147
8-2
B-148
B-138
B-141
B-116
B-144
B-149
B-120
B-132
B-118
B-140
B-151
B-155
B-150
8-1
8-1
8-2
7-1
8-3
21-20
8-3
Freescale Semiconductor, Inc.
8-2
For More Information On This Product,
MPC823 REFERENCE MANUAL
20-8
Go to: www.freescale.com
instructions, controlling the flow of,
instructions, definitions,
instructions, flow of,
instructions, invalid and preferred,
instructions, issuing,
instructions, serializing,
interdialog gap,
interface, development system
interfacing with slow devices,
interference, reducing,
interference, reduction,
interframe gap,
internal accesses (definition),
internal arbiter, enabling,
internal hard reset,
internal hard reset, causes of,
internal memory map register,
internal soft reset,
interrupt controller
interrupt generation,
interrupt handler code, notification of restartability,
interrupt latency, minimal,
interrupt structure (illustration),
interrupt vectors
interrupt, conditions for,
interrupt, recovery from,
interrupt, restarting after an,
interrupts
6-10
debug mode support,
trap enable mode,
memory map,
encoding,
generating,
classes,
configuring,
CPM interrupt controller,
definitions,
external,
from SCCx,
handling in SCCs,
highest priority,
implementation-specific
implementation-specific data TLB error,
implementation-specific data TLB miss,
implementation-specific instruction TLB error,
implementation-specific instruction TLB miss,
implementation-specific,
masking sources in the CPM,
memory management unit
20-20
11-48
11-47
breakpoint,
debug port unmaskable,
7-7
6-13
16-502
7-8
16-263
16-501
16-263
12-5
16-184
3-6
4-4
4-3
6-10
16-498
6-2
5-28
6-6
16-185
20-22
5-19
5-12
6-12
7-1
6-7
6-8
13-41
20-22
6-13
6-10
6-10
16-508
15-67
15-68
4-3
3-1
12-5
6-10
16-500
7-1
6-5
Index-15
11-48
11-47
Index