mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 193

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

9.2.1 Instruction Cache Control and Status Register
The instruction cache control and status register (IC_CST) is used to configure and access
the status of the instruction cache.
IEN—Instruction Cache Enable Status
This read-only bit indicates the status of the instruction cache. Any attempt to write to it is
ignored. You can enable or disable the instruction cache by writing to the CMD field.
Bits 1–3—Reserved
These bits are reserved and must be set to 0.
CMD—Command
The following commands can be written to the CMD field to control and configure the
instruction cache. The machine must be in privilege mode (MSR
Bits 7–9—Reserved
These bits are reserved and must be set to 0.
IC_CST
NOTE: — = Undefined.
RESET
RESET
FIELD
FIELD
SPR
SPR
R/W
R/W
BIT
BIT
0 = Instruction cache is disabled.
1 = Instruction cache is enabled.
000 = Reserved.
001 = CACHE ENABLE .
010 = CACHE DISABLE .
011 = LOAD & LOCK .
100 = UNLOCK LINE .
101 = UNLOCK ALL .
110 = INVALIDATE ALL .
111 = Reserved.
IEN
16
0
0
R
17
1
RESERVED
18
—
2
0
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CMD
R/W
21
5
0
22
6
23
7
RESERVED
560
560
—
RESERVED
0
24
—
8
0
25
9
CCER1
10
26
0
R
PA
CCER2
=1).
11
27
0
R
CCER3
12
28
0
R
Instruction Cache
13
29
RESERVED
14
30
—
0
15
31
9-5