mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 363

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

15.3 REGISTER MODEL
The status bits for each one of the memory banks are in the memory controller status
(MSTAT) register, which is used by the entire memory controller. Each of the eight memory
banks has a base register (BRx) and an option register (ORx). The MSTAT reports write-
protect violations that occur and parity errors for every bank. The base register contains a V
bit that indicates when the information for the chip-select is valid.
Each base register defines the starting address of its memory bank and each option register
defines the attributes for its memory bank. The option registers also define the initial address
multiplexing for a memory cycle controlled by a UPM. The machine A mode register (MAMR)
and machine B mode register (MBMR) define most of the global features for the
user-programmable machines.
The memory command register (MCR) and memory data register (MDR) are used to
initialize the UPM’s RAM array. The MAD field of the memory command register specifies
the location in the RAM array to be executed as defined by the MCR. The memory address
register (MAR) allows a specific address pattern to be output onto the A[6:31] signals. The
memory periodic timer prescaler register (MPTPR) defines the divisor of the BRGCLK used
as the memory periodic timer input clock.
ADDRESS COMPARATOR
BANK SELECT
FIELD
MS
ADDRESS,
ADDRESS TYPE
Figure 15-4. Basic Memory Controller Operation
Freescale Semiconductor, Inc.
For More Information On This Product,
INTERNAL/EXTERNAL MEMORY ACCESS REQUEST
MPC823 REFERENCE MANUAL
TIMING GENERATOR
Go to: www.freescale.com
PROGRAMMABLE
MACHINE A
SIGNALS
USER-
EXTERNAL SIGNALS
TIMING GENERATOR
PROGRAMMABLE
MACHINE B
MUX
SIGNALS
USER-
GENERAL-PURPOSE
CHIP-SELECT
MACHINE
Memory Controller
15-7