mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 785

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.22.15 SCCx ETHERNET CONTROLLER ERRORS. The SCCx Ethernet controller
reports frame reception and transmission error conditions using the channel buffer
descriptors, the error counters, and the SCCE–Ethernet register. The following transmission
errors can be detected by the SCCx Ethernet controller.
The following reception errors can be detected by the SCCx Ethernet controller:
• Transmitter Underrun Error—If this error occurs, the channel sends 32 bits to ensure a
• Carrier Sense Lost During Frame Transmission Error — When this error occurs and no
• Retransmission Attempts Limit Expired Error — When this error occurs, the channel
• Late Collision Error — When this error occurs, the channel stops transmitting the buffer,
• Heartbeat Error — Some transceivers have a self-test feature called “heartbeat” or
• Overrun Error—The SCCx Ethernet controller maintains an internal FIFO for receiving
• Busy Error—This error occurs when a frame has been received and discarded because
CRC error, stops transmitting the buffer, closes it, sets the UN bit in the TX buffer
descriptor, and sets TXE in the SCCE–Ethernet register. The channel resumes
transmission after it receives the RESTART TRANSMIT command.
collision is found in the frame, the channel sets the CSL bit in the TX buffer descriptor,
sets the TXE bit in the SCCE–Ethernet register, and continues the buffer transmission
as normal. No retries are performed after this error occurs.
stops transmitting the buffer, closes it, sets the RL bit in the TX buffer descriptor, and
sets the TXE bit. The channel resumes transmission after it receives the RESTART
TRANSMIT command.
closes it, sets the LC bit in the TX buffer descriptor, and sets the TXE bit. The channel
resumes transmission after it receives the RESTART TRANSMIT command. This error
is discussed further in the definition of the LCW bit in the PSMR–SCC Ethernet.
“signal quality error.” To signify a good self-test, the transceiver indicates a collision to
the MPC823 within 20 clocks after the Ethernet controller transmits a frame. This
indication does not imply a real collision error on the network, but is rather an indication
that the transceiver is still functioning properly. This is called the heartbeat condition.
If the HBC bit is set in the PSMR–SCC Ethernet and the MPC823 does not detect a
data. If a receiver FIFO overrun occurs, the channel writes the received data byte to the
internal FIFO over the previously received byte. The previous data byte and frame
status are lost. The channel closes the buffer, sets the OV bit in the RX buffer
descriptor, RXF in the SCCE–Ethernet register, and increments the discarded frame
counter. The receiver then enters hunt mode.
of a lack of buffers. The channel sets the BSY bit in the SCCE–Ethernet register and
increments the discarded frame counter.
heartbeat condition after transmitting a frame, then a heartbeat error occurs. In which
case, the channel closes the buffer, sets the HB bit in the TX buffer descriptor, and
generates a TXE interrupt if it is enabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
16-333