mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 722

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.19.6 EXCEPTIONS TO RFC 1549. The following beheviors do not conform to RFC
1549.
16.9.19.7 SCCx ASYNC HDLC IMPLEMENTATION. The following behaviors represent
the key aspects of the SCCx ASYNC HDLC controller.
• If an 0x7D is followed by a control character and the control character is not mapped,
• In addition to the abort sequence, frames are terminated by the following errors:
• If the invalid sequence is received, the first control escape character is discarded, and
• Flag Sequence—When transmitting, the controller automatically generates the opening
• Address Field—The address field is neither generated nor examined by the microcode
• Control Field—The control field is neither generated nor examined by the microcode
• Frame Check Sequence—When transmitting, the frame check sequence (CRC) is
• Encoding—The SCCx ASYNC HDLC controller only supports 8 data bits, one start bit,
• Time-Fill (Idling)—When transmitting, the SCCx ASYNC HDLC controller transmits
the control character itself is “modified” by the XOR process. The CRC check must
catch this exception. This is a case where the transmitter control character table differs
from the receiver.
the second is unconditionally exclusive-OR’ed with 0x20. This sequence is stored in the
buffer descriptor as 0x5D.
and closing flag for the frame. When receiving, the controller strips off the opening and
closing flag before writing the frame to memory. It receives frames with only one
“shared” flag between them and ignores multiple flags between frames.
while transmitting or receiving. The address field of the frame must be included in the
data buffer that the transmit buffer descriptor points to. Any address field compression,
expansion, or checking must be performed by the core.
while transmitting or receiving. The control field of the frame must be included in the
data buffer that the transmit buffer descriptor points to. Any control field compression,
expansion, or checking must be performed by the core.
automatically appended to the end of the frame before the closing flag is transmitted.
The frame check sequence is generated on the original frame before the transparency
characters, start/stop bits, or flags are added. The controller uses a 16-bit CRC-CCITT
polynomial. When receiving, the frame check sequence is automatically checked. The
frame check sequence is calculated after any transparency characters, start/stop bits,
and flags are removed. The controller uses a 16-bit CRC-CCITT polynomial.
one stop bit, and no parity. This must be programmed in the PSMR–SCC ASYNC
HDLC register so that bits 2 and 3 are set to 1 for proper operation.
IDLE characters when no data is available for transmission. When receiving, the SCCx
ASYNC HDLC controller ignores IDLE characters.
Carrier detect lost
Receiver overrun
Framing error
Break sequence
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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