mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 34

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Number
6-7.
6-8.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
9-1.
9-2.
10-1.
10-2.
11-1.
11-2.
11-3.
11-4.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10. Basic Flow Diagram Of A Burst Read Cycle ............................................... 13-17
Figure
Single Register Fixed-Point Load/Store Instructions..................................... 6-28
Number of Bus Cycles Needed For String Instruction Execution.................. 6-30
Example of a Data Cache Load ...................................................................... 8-4
Example of a Writeback Arbitration ................................................................. 8-5
Another Example of a Writeback Arbitration ................................................... 8-5
Example of a Private Writeback Bus Load ...................................................... 8-6
Example of an External Load .......................................................................... 8-7
Example of a Full History Buffer...................................................................... 8-8
Example of Branch Folding ............................................................................. 8-9
Example of Branch Prediction ....................................................................... 8-10
Instruction Cache Organization Block Diagram............................................... 9-3
Cache Data Path Block Diagram..................................................................... 9-4
Data Cache Organization ............................................................................. 10-2
Cache Data Path Block Diagram................................................................... 10-3
Block Diagram of Effective-to-Real Address Translation For 4K Pages ....... 11-3
Two Level Translation Table When MD_CTR(TWAM) = 1 ........................... 11-6
Two Level Translation Table When MD_CTR(TWAM) = 0 ........................... 11-7
Organization of the Memory Management Unit Registers .......................... 11-15
System Configuration and Protection Logic .................................................. 12-4
MPC823 Interrupt Structure .......................................................................... 12-5
Interrupt Table Handling Example............................................................... 12-11
Real-Time Clock Block Diagram ................................................................. 12-17
Periodic Interrupt Timer Block Diagram ...................................................... 12-22
Software Watchdog Timer Service State Diagram...................................... 12-26
Software Watchdog Timer Block Diagram .................................................. 12-27
Input Sample Window ................................................................................... 13-2
MPC823 Bus Signals .................................................................................... 13-3
Basic Flow Diagram of a Single Beat Read Cycle ........................................ 13-9
Single Beat Read Cycle–Basic Timing–Zero Wait States ........................... 13-10
Single Beat Read Cycle–Basic Timing–One Wait State ............................. 13-11
Basic Flow Diagram of a Single Beat Write Cycle....................................... 13-12
Single Beat Write Cycle–Basic Timing–Zero Wait States ........................... 13-13
Single Beat Write Cycle of One Wait State ................................................. 13-14
Single Beat, 32-Bit Data, Write Cycle From a 16-Bit Port Size ................... 13-15
Number of Bus Cycles Needed For Unaligned,
LIST OF ILLUSTRATIONS (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Title
MOTOROLA
Number
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