mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 314

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Bus Interface
13.4.1 Basic Transfers
The basic transfer protocol defines the sequence of actions that must occur on the MPC823
bus to perform a complete bus transaction. The chronological sequence or phase of a typical
bus transfer is as follows:
This protocol provides for an arbitration phase and an address and data transfer phase. The
arbitration phase specifies the master that initiates the next transaction. The address phase
specifies the address for the transaction and the transfer attributes that describe the
transaction. The data phase performs the transfer of data. It can transfer a single beat of
data (4 bytes or less) for nonburst operations, a 4-beat burst of data, an 8-beat burst of data,
or a 16-beat burst of data.
13.4.2 Single Beat Transfers
During the data transfer phase, data is transferred from master to slave on write cycles or
from slave to master on read cycles. On a write cycle, the master drives the data as soon
as it can, but never before the cycle following the address transfer phase. The master has
to take into consideration the “one dead clock cycle” when switching between drivers to
avoid electrical contention. The master can stop driving the data bus as soon as it samples
the TA line asserted on the rising edge of the CLKOUT. On a read cycle the master accepts
the data bus contents as valid at the rising edge of the CLKOUT in which the TA signal is
sampled asserted.
1. Arbitration
2. Address transfer
3. Data transfer
4. Termination
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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