mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 331

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

13.4.5 Transfer Alignment and Packaging
The MPC823 external bus only supports natural address alignment that forces the following
restrictions:
The MPC823 can perform operand transfers through its 32-bit data port. If the transfer is
controlled by the internal memory controller, the MPC823 can support 8- and 16-bit data port
sizes. The bus requires that the portion of the data bus used for a transfer to or from a
particular port size to be fixed. A 32-bit port must reside on data bus bits 0-31, a 16-bit port
must reside on bits 0-15, and an 8-bit port must reside on bits 0-7. The MPC823 always tries
to transfer the maximum amount of data on all bus cycles and for a word operation it always
assumes that the port is 32 bits wide at the beginning of the bus cycle. In Figure 13-18 and
Figure 13-19 and Table 13-2 and Table 13-3, the following operand conventions have been
adopted:
• Byte access can have any address alignment
• Half-word access must have address bit 31 equal to 0
• Word access must have address bits 30-31 equal to 0
• For burst access must have address bits 30-31 equal to 0
• OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte.
• The two bytes of a half-word operand are OP0 (most-significant) and OP1 or OP2
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the
(least-significant) and OP3, depending on the address of the access.
address of the access.
0
Note: Although this is a 32-bit machine, only 26 of the bits are visible outside the chip.
OP0
OP0
OP0
Figure 13-18. Internal Operand Representation
Freescale Semiconductor, Inc.
For More Information On This Product,
OP1
OP1
OP1
MPC823 REFERENCE MANUAL
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OP2
OP2
OP2
OP3
OP3
31
WORD
HALF-WORD
BYTE
External Bus Interface
13-25