mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 485

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.3.3.3 DSP EVENT REGISTER. For DSP interrupts, the memory-mapped SDMA status
register (SDSR) is used to generate maskable interrupts to the core. An interrupt is set when
the function finishes executing if the I bit is set in the function descriptor. There are two
interrupt events—DSP1 and DSP2—that are each associated with a corresponding chain.
A bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset
at a time.
SBER—SDMA Channel Bus Error (SDMA function)
When set, this bit indicates that an error caused the SDMA channel to terminate during a
read or write cycle. The SDMA bus error address can be read from the SDMA address
register, as described in Section 16.5.2.4 SDMA Address Register.
Bits 1–5—Reserved
These bits are reserved and must be set to 0.
DSP2—DSP Chain 2 Transmitter Interrupt (DSP function)
This bit is set when the chain 2 function finishes executing. However, the I bit must be set in
the function descriptor.
DSP1—DSP Chain 1 Receiver Interrupt (DSP function)
This bit is set when the chain 1 function finishes executing. However, the I bit must be set in
the function descriptor.
SDSR
RESET
FIELD
ADDR
R/W
BIT
SBER
R/W
0
0
Freescale Semiconductor, Inc.
1
For More Information On This Product,
MPC823 REFERENCE MANUAL
2
Go to: www.freescale.com
(IMMR & 0xFFFF0000) + 0x908
RESERVED
R/W
3
0
4
Communication Processor Module
5
DSP2
R/W
6
0
DSP1
R/W
7
0
16-33