mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1217

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

MPC823 Instruction Set—isync
isync
Definition
Description
FIELD
FIELD
BIT
BIT
16
0
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1
00000
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effects of all instructions executed by a processor. Executing an
isync instruction ensures that all instructions preceding the the
isync instruction have completed before the isync instruction
completes, except that memory accesses caused by those
instructions need not have been performed with respect to other
processors and mechanisms. It also ensures that no subsequent
instructions are initiated by the processor until after the isync
instruction completes. Finally, it causes the processor to discard
any prefetched instructions, with the effect that subsequent
instructions will be fetched and executed in the context
established by the instructions preceding the isync instruction.
The isync instruction has no effect on the other processors or on
their caches. This instruction is context synchronizing.
Context synchronization is necessary after certain code
sequences that perform complex operations within the
processor. These code sequences are usually operating system
tasks that involve memory management. For example, if an
instruction “A” changes the memory translation rules in the
memory management unit (MMU) , the isync instruction must be
executed so that the instructions following instruction “A” will be
discarded from the pipeline and refetched according to the new
translation rules. This instruction is context synchronizing.
Other registers altered:
Instruction Synchronize
The isync instruction provides an ordering function for the
POWERPC ARCHITECTURE
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MPC823 REFERENCE MANUAL
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None
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5
LEVEL
VEA
22
6
23
7
00000
24
8
25
9
SUPERVISOR
150
10
26
11
27
OPTIONAL
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00000
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MOTOROLA
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FORM
XL
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0