mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1105

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Development Capabilities and Interface
CHBMSK—Byte Mask for Comparator H
Bits 30–31—Reserved
These bits are reserved and must be set to 0.
20.6.2.7 LOAD/STORE SUPPORT AND-OR CONTROL REGISTER. The load/store
support AND-OR control (LCTRL2) register is used to control the bit masks for load/store
data comparisons. Watchpoint programming consists of three control register fields—
LWxIA, LWxLA, and LWxLD. All three conditions must be detected to assert a watchpoint.
The reset value of this register is 0x00000000.
LW0EN—First Load/Store Watchpoint Enable
LW0IA—First Load/Store Watchpoint I-Address Watchpoint Selection
LCTRL2
RESET
RESET
FIELD
FIELD
SPR
SPR
R/W
R/W
BIT
BIT
0000 = All bytes are not masked.
0001 = Last byte of the word is masked.
•
•
•
1111 = All bytes are masked.
0 = Watchpoint not enabled (reset value).
1 = Watchpoint enabled.
00 = First instruction watchpoint.
01 = Second instruction watchpoint.
10 = Third instruction watchpoint.
11 = Fourth instruction watchpoint.
LW0E
LW1L
ADC
R/W
R/W
16
0
N
0
0
17
1
LW1LD
LW0IA
R/W
R/W
0
0
18
2
Freescale Semiconductor, Inc.
LW0IA
LW1L
For More Information On This Product,
DDC
R/W
R/W
DC
19
3
0
0
OMSK
BRKN
R/W
20
MPC823 REFERENCE MANUAL
4
0
LW0LA
R/W
0
Go to: www.freescale.com
21
5
LW0L
ADC
R/W
22
6
0
23
7
LW0LD
R/W
157
RESERVED
157
0
R/W
24
8
0
LW0L
DDC
R/W
25
9
0
LW1E
R/W
10
26
N
0
11
27
LW1IA
R/W
0
DLW0
R/W
12
28
EN
0
LW1IA
DLW1
R/W
R/W
DC
13
29
EN
0
0
MOTOROLA
SLW0
R/W
14
30
EN
0
LW1LA
R/W
0
SLW1
R/W
15
31
EN
0