mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 793

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

PAD—Short Frame Padding
This bit is only valid when the L bit is set. Otherwise, it is ignored.
W—Wrap (Final Buffer Descriptor in Table)
I—Interrupt
L—Last
TC—TX CRC
This bit is valid only when the L bit is set. Otherwise, it is ignored.
DEF—Defer Indication
This bit indicates that this frame had a collision before it was sent. It is useful for channel
statistics. The SCCx Ethernet controller writes this bit after it finishes transmitting the
associated data buffer.
HB—Heartbeat
This bit indicates the collision input was not asserted within 20 transmit clocks after
transmission. It cannot be set unless the HBC bit is set in the PSMR–SCC Ethernet. The
SCCx Ethernet controller writes this bit after it finishes transmitting the associated data
buffer.
0 = Do not add pads to short frames.
1 = Add pads to short frames. Pad bytes are inserted until the length of the transmitted
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
0 = No interrupt is generated after this buffer is serviced.
1 = The TXB or TXE bit is set in the SCCE–Ethernet register after this buffer is
0 = This is not the last buffer in the transmit frame.
1 = This is the last buffer in the transmit frame.
0 = End transmission immediately after the last data byte.
1 = Transmit the CRC sequence after the last data byte.
frame equals the MINFLR and they are stored in pads in the parameter RAM.
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
serviced. These bits can cause interrupts if they are enabled.
Note: The TX buffer descriptor table must contain more than one buffer descriptor in
SCCx Ethernet mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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