mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1148

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Terminology
exception
execution serialization
execution stream
fetch serialization
half-word
internal bus
interrupt
latency
little-endian
master
memory controller
An error, unusual condition, or external signal that can set a status bit. It may or may
not cause an interrupt, depending on whether or not the corresponding interrupt is
enabled.
Instruction issue is halted until all instructions that are currently in progress complete
execution, all internal pipeline stages and instruction buffers have emptied, and all
outstanding memory transactions have completed.
The combination of instructions and data on which the core operates.
Instruction fetch is halted until all instructions currently in the processor have completed
execution, including the prefetched instructions waiting to be issued. The machine after
fetch serialization is said to be completely synchronized.
A half-word consists of 2 bytes or 16 bits.
The bus connecting the core and system interface unit.
The act of changing the machine state register and other parts of the machine state in
response to an exception.
The interval from the time an instruction begins execution until it produces a result that
is available for use by a subsequent instruction.
Little-endian byte ordering assigns the lowest address to the lowest-order (rightmost)
eight bits of the scalar. The little end of the scalar, considered a binary number, comes
first in memory.
A device on the bus that requests bus ownership and initiates the bus cycles.
A functional logic section of the MPC823. Its primary function is to provide the controls
for the external bus memories and I/O devices.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
MOTOROLA