mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 672

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
A—Address
CM—Continuous Mode
ID—Buffer Closed on Reception of Idles
This bit indicates that the buffer is closed because a programmable number of consecutive
idle sequences (MAX_IDL) was received.
AM—Address Match
This bit is only significant if the address bit is set and the automatic multidrop mode is
selected in the UM field of the PSMR-SCC UART. After an address match, this bit defines
the address character that matched the address character that you defined, which enables
the SCCx UART controller to receive data.
BR—Break Received
This bit indicates that a break sequence has been received at the same time that data is
being received into this buffer.
FR—Framing Error
This bit indicates that a character with a framing error has been received and located in the
last byte of this buffer. A framing error is a character without a stop bit. A new receive buffer
is used to receive more data.
PR—Parity Error
This bit indicates that a character with a parity error has been received and located in the
last byte of this buffer. A new receive buffer is used to receive more data.
OV—Overrun
This bit indicates that a receiver overrun has occurred while the SCCx UART controller was
receiving a message.
0 = The buffer only contains data.
1 = When operating in manual multidrop mode, this bit indicates that the first byte of
0 = Normal operation.
1 = The E bit is not cleared by the communication processor module after this buffer
0 = The address matched the value in UADDR2 of the SCCx UART parameter RAM.
1 = The address matched the value in UADDR1 of the SCCx UART parameter RAM.
this buffer contains an address byte. The address comparison must be
implemented in the software. In automatic multidrop mode, this bit indicates that
the buffer descriptor contains a message that was received immediately after an
address was recognized in UADDR1 or UADDR2. This address is not written into
the receive buffer.
descriptor is closed, thus allowing the associated data buffer to be automatically
overwritten next time the communication processor module accesses this buffer
descriptor. However, the E bit is cleared if an error occurs during reception,
regardless of how the CM bit is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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