mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 232

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
11.6 PROGRAMMING THE MEMORY MANAGEMENT UNIT
The memory management unit implements specific operations using control and status
registers, which can be accessed with the PowerPC mtspr/mfspr instructions. In addition,
the PowerPC tlbie and tlbia architecture instructions are supported. The memory
management unit registers must be accessed when both MSR
similar restriction exists for the tlbie and tlbia instructions.
CONFIGURATION REGISTERS:
MI_CTR
MI_AP
TABLE WALK REGISTERS:
MI_EPN
MI_TWC
MI_RPN
DEBUG REGISTERS:
MI_DCAM
MI_DRAM0
MI_DRAM1
Figure 11-4. Organization of the Memory Management Unit Registers
INSTRUCTION MMU REGISTERS
Instruction MMU Table Walk Control
Instruction MMU Access Protection
Instruction MMU Effective Address
Instruction MMU Real Address
Instruction MMU Debug RAM0
Instruction MMU Debug RAM1
Instruction MMU Debug CAM
Instruction MMU Control
Freescale Semiconductor, Inc.
For More Information On This Product,
M_CASID
M_TWB
M_TW
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Current Address Space ID
MMU Table Walk Scratch
MMU Table Walk Base
MD_CTR
MD_AP
MD_EPN
MD_TWC
MD_RPN
MD_DCAM
MD_DRAM0
MD_DRAM1
DATA MMU REGISTERS
Data MMU Table Walk Control
Data MMU Access Protection
Data MMU Effective Address
Data MMU Real Address
Data MMU Debug RAM0
Data MMU Debug RAM1
Data MMU Debug CAM
IR
Data MMU Control
=0 and MSR
Memory Management Unit
DR
=0. No
11-15

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