mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 91

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Reset
4.1.3.4 DEBUG PORT HARD RESET. When the development port receives a hard reset
request from the development tool, an internal hard reset sequence is generated. In this
case, the development tool must reconfigure the debug port. See
Section 20.2.1.2.6 Detecting the Trace Window End Address for more information.
4.1.3.5 JTAG RESET. When the JTAG logic asserts the JTAG soft reset signal, an internal
soft reset sequence will be generated.
4.1.4 External Soft Reset
When an external SRESET is asserted, the core starts driving the SRESET pin. When the
timer expires, after 512 cycles, the debug port configuration is sampled from the DSDI and
DSCK pins and the core stops driving the pin. An external pull-up resistor should drive it high
and once it is negated a 16-cycle period passes before the presence of an external soft reset
is tested.
4.1.5 Internal Soft Reset
When the core finds a reason to assert SRESET, it starts driving the SRESET pin. When
the timer expires, after 512 cycles, the debug port configuration is sampled from the DSDI
and DSCK pins and the core stops driving the SRESET pin. An external pull-up resistor
should drive the pin high and once it is negated a 16-cycle period passes before the
presence of an external soft reset is tested. JTAG and the debug port cause an internal soft
reset.
4.1.5.1 DEBUG PORT SOFT RESET. When the development port receives a soft reset
request from the development tool, an internal soft reset sequence is generated. In this case
the development tool must reconfigure the debug port. See Section 20.2.1.2.6 Detecting
the Trace Window End Address for more information.
Note: It is recommended that you connect TRST to ground (if you don't use JTAG) or
to PORESET through a diode. The problem with the connection to HRESET is
that if at power up the JTAG logic blocks the PORESET signal from propagating
into the chip (since the logic is not initialized yet), this will prevent HRESET from
asserting, which leaves the JTAG logic (and the whole device) uninitialized.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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