mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 758

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.21.7 SCCx TRANSPARENT CONTROLLER ERRORS. The serial communication
controllers report message reception and transmission errors using the channel buffer
descriptors, the error counters, and the SCCE–Transparent register. The following
transmission errors can be detected by the SCCx Transparent controller.
The following reception errors can be detected by the SCCx Transparent controller.
16.9.21.8 SCCx TRANSPARENT MODE REGISTER. Since all transparent mode
selections are in the GSMR_H, the PSMR is not used by the SCCx Transparent controller.
If transparent mode is only selected for the transmitter/receiver, then the transmitter/receiver
can be programmed to support another protocol. In such a case, you can use the PSMR for
the other protocol.
• Transmitter Underrun — When this error occurs, the channel stops transmitting the
• CTS Lost During Message Transmission — When this error occurs, the channel stops
• Overrun — The serial communication controllers maintain an internal FIFO for receiving
• CD Lost During Message Reception — When this error occurs, the channel stops
buffer, closes it, sets the UN bit of the TX buffer descriptor, and generates the TXE
interrupt if it is enabled. The channel resumes transmission after the RESTART
TRANSMIT command is received. Underrun occurs after a transmit frame for which the
L bit of the TX buffer descriptor was not set. In this case, only the TXE bit is set.
Underrun cannot occur between transparent frames.
transmitting the buffer, closes it, sets the CT bit of the buffer descriptor, and generates
the TXE interrupt if it is enabled. The channel resumes transmission after the
RESTART TRANSMIT command is received.
data. The communication processor module starts programming the SDMA channel if
the data buffer is in external memory and updating the CRC when 8 or 32 bits are
received in the FIFO. If a FIFO overrun occurs, the serial communication controllers
write the received data byte to the internal FIFO over the previously received byte. The
previous character and its status bits are lost. Afterwards, the channel closes the buffer,
sets the OV bit of the RX buffer descriptor, and generates the RX interrupt if it is
enabled. The receiver immediately enters hunt mode.
receiving messages, closes the buffer, sets the CD bit of the RX buffer descriptor, and
generates the RX interrupt if it is enabled. This error has the highest priority, the rest of
the message is lost, and no other errors are checked in the message.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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