mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 176

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

SRR1—Save/Restore Register 1
MSR—Machine State Register
DSISR—Data/Storage Interrupt Status Register
DAR—Data Address Register
Set to the effective address of the data access that caused the interrupt.
Some instruction TLB registers are set to the values described in
Section 11 Memory Management Unit. Execution resumes at offset x’01400’ from the
base address indicated by MSR
7.3.7.3.15 Implementation-Specific Debug Register. An implementation-specific debug
interrupt occurs as a result of one of the following conditions:
• When there is an internal breakpoint match (for more details, refer to
• When a peripheral breakpoint request is presented to the interrupt mechanism.
• When the development port request is presented to the interrupt mechanism. Refer to
1–4
10–15
Other
IP
ME
LE
Other
0
1
2–3
4
5
6
7–31
Section 20.3 Generating Watchpoints And Breakpoints).
Section 20 Development Capabilities and Interface for details on how to generate
the development port request.
Set to 0.
Set to 0.
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
No change.
No change.
Bits are copied from the ILE.
Set to 0.
Set to 0.
Set to 1 if the translation of an attempted access is not found in the translation
tables. Otherwise, set to 0.
Set to 0.
Set to 1 if the storage access is not permitted by the protection mechanism;
otherwise set to 0.
Set to 0.
Set to 1 for a store operation and to 0 for a load operation.
Set to 0.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
IP
.
Go to: www.freescale.com
PowerPC Architecture Compliance
RI
.
7-15