mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 695

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

E—Empty
Bits 1, 7, and 9—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
I—Interrupt
L—Last in Frame
This bit is set by the SCCx HDLC controller when this buffer is the last one in a frame. This
implies the reception of a closing flag or reception of an error, in which case one or more of
the CD, OV, AB, and LG bits are set. The SCCx HDLC controller writes the number of frame
octets to the DATA LENGTH field.
NOTE:
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
0 = The data buffer associated with this RX buffer descriptor has been filled with data
1 = The data buffer associated with this buffer descriptor is empty or is currently
0 = This is not the last buffer descriptor in the RX buffer descriptor table.
1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer
0 = The RXB bit is not set after this buffer is used, but RXF operation remains
1 = The RXB or RXF bit in the SCCE–HDLC register is set when the SCCx HDLC
0 = This buffer is not the last one in a frame.
1 = This buffer is the last one in a frame.
You are only responsible for initializing the items in bold.
or reception has been aborted because of an error condition. The core is free to
examine or write to any fields of this RX buffer descriptor. The communication
processor module does not use this buffer descriptor as long as the E bit is zero.
receiving data. This RX buffer descriptor and its associated receive buffer are
owned by the communication processor module. Once the E bit is set, the core
must not write any fields of this RX buffer descriptor.
is used, the communication processor module receives incoming data into the first
buffer descriptor that RBASE points to in the table. The number of RX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
unaffected.
controller uses this buffer. These two bits can cause interrupts if they are enabled.
0
E
RES
1
W
2
Freescale Semiconductor, Inc.
For More Information On This Product,
3
I
MPC823 REFERENCE MANUAL
4
L
Go to: www.freescale.com
F
5
RX DATA BUFFER POINTER
CM
6
DATA LENGTH
RES
7
DE
8
RES
9
Communication Processor Module
LG
10
NO
11
AB
12
CR
13
OV
14
16-243
CD
15