mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 315

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
External Bus Interface
13.4.2.1 SINGLE BEAT READ FLOW. The basic read cycle begins with a bus arbitration,
followed by the address transfer and the data transfer. The handshakes are illustrated in the
following diagrams as applicable to the fixed transaction protocol.
MASTER
SLAVE
REQUEST BUS (BR)
RECEIVES BUS GRANT (BG) FROM ARBITER
ASSERTS BUS BUSY (BB) IF NO OTHER MASTER IS DRIVING
ASSERT TRANSFER START (TS)
DRIVES ADDRESS AND ATTRIBUTES
RECEIVES ADDRESS
RETURNS DATA
ASSERTS TRANSFER ACKNOWLEDGE (TA)
RECEIVES DATA
Figure 13-3. Basic Flow Diagram of a Single Beat Read Cycle
MPC823 REFERENCE MANUAL
13-9
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