mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 312

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Bus Interface
TRANSFER CYCLE TERMINATION
MNEMONIC
DP[0:3]
TEA
TA
BI
Table 13-1. Bus Interface Signals (Continued)
Freescale Semiconductor, Inc.
PINS
For More Information On This Product,
4
1
1
1
MPC823 REFERENCE MANUAL
ACTIVE
High
Low
Low
Low
Go to: www.freescale.com
I/O
I/O
O
O
O
O
I
I
I
I
Parity Bus —Each parity signal corresponds to each
one of the data bus lanes:
Data Bus Byte
D[0:7]
D[8:15]
D[16:23]
D[24:31]
Driven by the MPC823 when it owns the external bus
and has initiated a write transaction to a slave device.
Each parity signal has the parity value (even or odd)
of the corresponding data bus byte. For single beat
transactions, if external A[6:31] and TSIZ[0:1] do not
select the byte lanes for transfer, they will not have a
valid parity line.
Driven by the slave in a read transaction. Each parity
signal is sampled by the MPC823 and checked (if
enabled) against the expected value parity value
(even or odd) of the corresponding data bus byte. For
single beat transactions, if external A[6:31] and
TSIZ[0:1] do not select the byte lanes for transfer,
they will not be sampled by the MPC823 and its parity
signals will not be checked.
Transfer Acknowledge—Driven by the slave device
the current transaction was addressed to. It indicates
that the slave has received the data on the write cycle
or returned the data on the read cycle. If the
transaction is a burst, TA must be asserted for each
one of the transaction beats.
Driven by the MPC823 when the slave device is
controlled by the on-chip memory controller.
Transfer Error Acknowledge—Driven by the slave
device the current transaction was addressed to. It
indicates that an error condition has occurred during
the bus cycle.
Driven by the MPC823 when the internal bus monitor
detects an erroneous bus condition.
Burst Inhibit —Driven by the slave device the current
transaction was addressed to. It indicates that the
current slave does not support burst mode.
Driven by the MPC823 when the slave device is
controlled by the on-chip memory controller.
Parity Line
DP0
DP1
DP2
DP3
DESCRIPTION
MOTOROLA