mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 542

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.6.1 Features
The following is a list of the MPC823 IDMA’s main features:
16.6.2 IDMA Interface Signals
The MPC823 IDMA has two dedicated control signals per channel—DMA request and DMA
acknowledge. IDMA accepts DMA requests from the DREQ1 and DREQ2 signals and
acknowledges the request with the SDACK1 and SDACK2 signals. The peripheral used with
these signals can either be a source or destination of the IDMA transfers. The DREQx
signals are also used for memory-to-memory request generation and, in this case, must be
connected to the timer that controls the transfer.
16.6.2.1 DREQx AND SDACKx. These are the handshake signals between the MPC823
and the peripheral that needs to be serviced. When the peripheral asks for IDMA service, it
asserts DREQx and the MPC823 begins the IDMA process. While the service is in progress,
SDACKx is asserted during accesses to the device. DREQx can be configured to be either
edge- or level-sensitive by programming the DRxM field in the RCCR. The DRQP field in the
RCCR control IDMA channel priority in relation to the serial channels. To enable the DREQx
signals, the corresponding DREQx bit in the PCSO register must be set. When the DREQx
signals are configured as edge-sensitive requests, the edge on which a request is generated
is controlled by the corresponding EDMx bit in the PCINT register. For more information
about the Port C registers, see Section 16.14.9 Port C Registers.
16.6.3 IDMA Operation
Every IDMA operation involves the following series of events—IDMA channel initialization,
data transfer, and block termination. In the initialization phase, the core loads the
IDMA-specific parameter RAM with control information, initializes the IDMA buffer
descriptors, and starts the channel. In the transfer phase, IDMA accepts requests for
operand transfers and provides addressing and bus control for the transfers. The
termination phase occurs when the operation is complete and IDMA interrupts the core if
interrupts are enabled. To initialize a block transfer operation, you must initialize the IDMA
registers. The IDMA buffer descriptors must be initialized with information describing the
data block, device type, and other special control options. Refer to Section 16.6.3.2 IDMA
Parameter RAM Memory Map and Section 16.6.3.6 IDMA Commands for more details.
• Two independent, fully programmable DMA channels
• Dual address or single address transfers with 32-bit address and data capability
• 32-bit byte transfer counters
• 32-bit address pointers that can increment or remain constant
• Efficient operand packing and unpacking for dual address transfers
• All bus-termination modes are supported
• Provides DMA handshake for cycle steal and burst transfers
• Buffer handling modes (auto buffer and buffer chaining)
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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