mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 214

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

10.4.2.1 COPYBACK MODE
In copyback mode, write operations do not necessarily update the external memory. For this
reason, copyback mode is the preferred mode of operation when it is necessary to keep bus
bandwidth usage and power consumption at a minimum. The possible outcomes of a data
cache write in copyback mode are:
• Write Hit to Modified Line—Data is simply written into the cache with no state transition.
• Write Hit to Unmodified Line—Data is written into the cache and the line is marked
• Write Miss—A line in the cache is selected to hold the data that is fetched from memory.
The LRU of the set is updated to point to the way holding the hit data.
modified. The LRU of the set is updated to point to the way holding the hit data.
The selection algorithm gives first priority to invalid lines if both lines are invalid the way
zero line is selected first. If neither of the two candidate lines in the selected set is
invalid, then one of the lines is selected by the LRU algorithm for replacement. If the
selected line is valid-modified (dirty), it is kept in a special buffer to be written out
(flushed) to memory at a later time.
Subsequently, the address of the missed entry is sent to the system interface unit with
After the line with the requested data has been brought from memory, the dirty line kept
a request to retrieve the cache line. The system interface unit arbitrates for the bus and
initiates a 4-word burst transfer read request. The transfer begins with the aligned word
containing the missed data (the critical word first), followed by the remaining word in the
line, then by the word at the beginning of the line (wraparound). As the missed word is
received from the bus, it is merged with the data to be written. When the line has been
fully received, it is written into the cache. Once the line fill is complete, the new store
data is written into the cache and the line is marked modified-valid (dirty). At this point,
if the machine stalls while waiting for the store to complete, execution is allowed to
resume. The data cache does not support further requests until after the whole line
arrives.
in the buffer is sent to the system interface unit to be written out (flushed) to memory.
The data cache can support further requests as long as they hit in the cache while
flushing the dirty line to memory. If a bus error is detected during a fetch of the missed
line (even on a word not accessed by the load/store unit) the cache line is not modified
and a machine check interrupt is generated. If a bus error is detected during the dirty
line flush, a machine check interrupt is generated (the dirty line flush error is an
imprecise interrupt). For more information about reading the address and data of a line,
see Section 10.3.1.2 PowerPC Virtual Environment Architecture (Book II).
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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