mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 475

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
16.2.6.5 RISC TIMER EVENT REGISTER. The 16-bit RISC timer event register (RTER) is
used to report events recognized by the 16 timers and to generate interrupts. However, an
interrupt is only generated if the RISC timer table bit is set in the CPM interrupt mask
register. More than one bit can be cleared once.
TMR0–15—Timer 0–15
16.2.6.6 RISC TIMER MASK REGISTER. This 16-bit read/write RISC timer mask register
(RTMR) is used to enable interrupts that can be generated in the RTER. If a bit is set, it
enables the corresponding interrupt in the RTER. If a bit is cleared, this register masks the
corresponding interrupt in the RTER. However, an interrupt is only generated if the R-TT bit
is set in the CPM interrupt mask register (CIMR), which is described in
Section 16.15.5.3 CPM Interrupt Mask Register.
TMR0–15—Timer 0–15
RTER
RTMR
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = No effect.
1 = Clears a bit in the register.
0 = Masks the corresponding interrupt in the RTER.
1 = Enables the corresponding interrupt in the RTER.
TMR15
TMR15
R/W
R/W
0
0
0
0
TMR14
TMR14
R/W
R/W
1
1
0
0
TMR13
TMR13
R/W
R/W
2
2
0
0
Freescale Semiconductor, Inc.
TMR12
TMR12
For More Information On This Product,
R/W
R/W
3
3
0
0
TMR11
TMR11
R/W
R/W
MPC823 REFERENCE MANUAL
4
4
0
0
Go to: www.freescale.com
TMR10
TMR10
R/W
R/W
5
5
0
0
TMR9
TMR9
R/W
R/W
6
6
0
0
(IMMR & 0xFFFF0000) + 0x9D6
(IMMR & 0xFFFF0000) + 0x9DA
TMR8
TMR8
R/W
R/W
7
7
0
0
TMR7
TMR7
R/W
R/W
8
8
0
0
TMR6
TMR6
R/W
R/W
9
9
0
0
Communication Processor Module
TMR5
TMR5
R/W
R/W
10
10
0
0
TMR4
TMR4
R/W
R/W
11
11
0
0
TMR3
TMR3
R/W
R/W
12
12
0
0
TMR2
TMR2
R/W
R/W
13
13
0
0
TMR1
TMR1
R/W
R/W
14
14
0
0
16-23
TMR0
TMR0
R/W
R/W
15
15
0
0

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