mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 911

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
2
16.13.3.2.1 Write to Master. If an external master requests a write operation, the I
C
controller acknowledges the received data and writes it into a receive buffer using the next
available RX buffer descriptor until the next start or stop condition is detected.
After transmitting each data byte, the master checks for the acknowledge bit from the slave.
If an overrun condition occurs on the slave receiver, it will fail to acknowledge a byte and the
transmission will abort. An overrun condition occurs when more data is transmitted than the
2
slave can receive. A maskable interrupt may be issued by the I
C controller at the conclusion
of a normal or errant reception.
2
To prepare the I
C controller in slave mode for data reception, you must configure one or
more RX buffer descriptors to receive the data from the master. Set the E bit in the RX buffer
descriptors to prepare them to receive data. Other RX buffer descriptor control bits, such as
W and I, may also be set. You must then set the STR bit in the I2COM register to prepare
the slave to respond to the master.
2
16.13.3.2.2 Read from Master. If an external master requests a read operation, the I
C
controller will acknowledge the newly received byte containing the slave address and read
bit (R/W = 1), but only if the transmitter FIFO has been loaded by the SDMA channel.
If the transmitter is ready, the slave starts transmitting on the next clock pulse following the
acknowledge. Otherwise, the transaction is aborted and a maskable TX error interrupt may
be issued to notify the software to prepare transmit data for another attempt. A maskable
interrupt may be issued upon normal completion of transmission or after other transmission
errors occur. If an underrun condition occurs, the slave transmits ones until a stop condition
is detected. An underrun occurs if the slave device does not transmit all of the data
requested by the master.
2
To prepare the I
C controller in slave mode to transmit data, you must configure one or more
TX buffer descriptors to transmit the data to the master. Set the E bit in the RX buffer
descriptors to prepare them to receive data. Other TX buffer descriptor control bits, such as
W, I, and L, may also be set. You must then set the STR bit in the I2COM register to prepare
the slave to respond to the master.
MPC823 REFERENCE MANUAL
16-459
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