mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1277

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

MPC823 Instruction Set—sraw
sraw
Assembler Syntax
Definition
Operation
Description
FIELD
FIELD
BIT
BIT
16
0
17
1
18
B
2
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31
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19
3
sraw.
rA
of bits specified by rB[27–31]. Bits shifted out of position 31 are
lost. The result is padded on the left with sign bits before being
placed into rA. If rB[26] = 1, then rA is filled with 32 sign bits (bit
0) from rS. CR0 is set based on the value written into rA.
XER[CA] is set if rS contains a negative number and any 1 bits
are shifted out of position 31; otherwise XER[CA] is cleared. A
shift amount of zero causes XER[CA] to be cleared.
The sraw instruction, followed by addze, can by used to divide
quickly by 2
independent of mode.
Other registers altered:
sraw
Shift Right Algebraic Word
n
If rB[26] = 0,then the contents of rS are shifted right the number
20
MPC823 REFERENCE MANUAL
4
rB[27-31]
ROTL(rS,
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
Affected: CA
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21
5
n
. The setting of the XER[CA] bit, by sraw, is
rA,rS,rB (Rc = 0)
rA,rS,rB (Rc = 1)
22
6
n
)
23
7
24
S
8
25
9
792
10
26
11
27
12
28
13
29
A
MOTOROLA
14
30
RC
15
31