mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 413

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
The uppermost byte select (BS0) signal indicates that the most-significant eight bits of the
data bus (D0-7) contain valid data during a cycle and the upper-middle byte-select (BS1)
indicates that the upper-middle eight bits of the data bus (D[8-15]) signal contain valid data
during a cycle. The lower-middle byte-select (BS2) indicates that the lower-middle eight bits
of the data bus (D[16-23]) contain valid data during a cycle and the lowest byte-select (BS3)
indicates that the least-significant eight bits of the data bus (D[24-31]) contain valid data
during a cycle. The manner in which the BSx signals affect 32-, 16-, and 8-bit accesses is
shown in Table 15-5. It must be noted that for a periodic timer request and a memory
command request, the BSx signals are only determined by the port size of the bank.
Byte
Half-Word
Word
TRANSFER
SIZE
TSIZx
0
0
0
0
1
1
0
1
1
1
1
0
0
0
ADDRESS
A30 A31 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3
0
0
1
1
0
1
0
Freescale Semiconductor, Inc.
For More Information On This Product,
0
1
0
1
0
0
0
Table 15-5. Enabling Byte-Selects
MPC823 REFERENCE MANUAL
X
X
X
32-BIT PORT SIZE
Go to: www.freescale.com
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16-BIT PORT SIZE
X
X
X
X
X
X
X
X
X
X
X
X
8-BIT PORT SIZE
Memory Controller
15-57

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