mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 274

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
12.3 INTERRUPT CONFIGURATION
Many aspects of MPC823 system configuration are controlled by the SIU module
configuration register (SIUMCR). The SIUMCR primarily controls the external bus arbitration
logic, external master support, and pin multiplexing. See Section 12.12.1.1 SIU Module
Configuration Register for more information.
12.3.1 The Interrupt Structure
The system interface unit receives interrupts from internal sources, such as the periodic
interrupt timer, real-time clock, communication processor module (CPM), and the external
IRQx pins. The MPC823 interrupt structure is illustrated in Figure 12-2.
If it is programmed to generate an interrupt, the software watchdog timer always generates
a nonmaskable interrupt (NMI) to the core. The external IRQ0 pin will generate a
nonmaskable interrupt as well.
IRQ[0:7]
SYSTEM INTERFACE UNIT
EDGE
DET
INTERRUPT CONTROLLER
Freescale Semiconductor, Inc.
Figure 12-2. MPC823 Interrupt Structure
CPM / LCD/VIDEO
For More Information On This Product,
DECREMENTER
MPC823 REFERENCE MANUAL
REAL-TIME
INTERRUPT
TIMEBASE
PERIODIC
PCMCIA
CLOCK
Go to: www.freescale.com
TIMER
DEBUG
SOFTWARE
WATCHDOG
TIMER
LEVEL 7
LEVEL 6
LEVEL 5
LEVEL 4
LEVEL 3
LEVEL 2
LEVEL 1
LEVEL 0
IRQ0
GEN
NMI
System Interface Unit
IREQ
DEBUG
DECREMENTER
POWERPC
NMI
CORE
12-5

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