mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1092

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

In trap enable mode the “Valid Data from CPU” and “CPU Interrupt” status cannot occur. Out
of debug mode, the sequencing error encoding indicates that the transmission from the
external development tool was a debug mode transmission. When a sequencing error
occurs, the development interface port ignores the data shifted in while the sequencing error
is shifting out and being treated as a no operation (NOP) function. The null output encoding
indicates that the previous transmission did not have any associated errors. Out of debug
mode, ready will be asserted at the end of each transmission. If debug mode is not enabled
and transmission errors are guaranteed not to occur, the status output is not needed.
20.4.3.8 DEBUG MODE. In debug mode, the development interface port starts
communicating by setting the DSDO field low to indicate that the core is trying to read an
instruction from the DPIR or data from the DPDR. When the core writes data to the port to
be shifted out, the READY bit is not set. The port waits for the core to read the next
instruction before asserting ready. This allows duplex operation of the serial port while
allowing the port to control all transmissions from the external development tool. After
detecting this ready status, the external development tool begins transmitting the
development interface port with a START bit (logic high) on the DSDI pin.
In debug mode, the 35 bits of the development interface port shift register are interpreted as
a START/READY bit, a MODE/STATUS bit, a CONTROL/STATUS bit, and 32 bits of data.
All instructions and data for the core are transmitted with the mode bit cleared, thus
indicating a 32-bit DATA field. The encoding of data shifted into the development interface
port shift register through the DSDI pin is shown in Table 20-11.
NOTE: For freeze status, 0 means the core is in normal mode and 1 means the core is in debug mode. For download
READY
(0)
(0)
(0)
(0)
status, 0 means the download is in progress and 1 means the core is in normal mode.
STATUS [0:1]
0
0
1
1
Table 20-10. Status/Data Shifted Out of DPS Register
0
1
0
1
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Freeze
Status
BIT 0
MPC823 REFERENCE MANUAL
Procedure
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Download
Progress
BIT 1
In
DATA
DATA
DEPENDING ON THE INPUT
BITS 2-31 OR 2-6,
MODE
All 1’s
All 1’s
All 1’s
Development Capabilities and Interface
Valid Data From Core
Sequencing Error
Core Interrupt
FUNCTION
Null
20-37